View SIC413CB-T1-E3_3291921.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 1 microbuck tm sic413 4-a, 26-v integrated sy nchronous buck regulator description the sic413 is an integrated, dc-to-dc power conversion solution with built-in pwm-optimized high- and low-side n-channel mosfets and advanced pwm controller. the sic413 provides a quick and easy to use pol voltage regulation solution for a wide range of applications. vishay siliconix?s proprietary packa ging technology is used to optimize the power stage and minimize power losses associated with parasitic impedances and switching delays. the co-packaged gen iii trenchfet power mosfet devices deliver higher efficiency than lateral dmos monolithic solutions. features ? integrated pwm controller and gen iii trench mosfets ? quick and easy single chip converter ? integrated current sense ? cycle by cycle over-current protection ? built-in bootstrap diode ? output over-voltage protection ? under voltage lockout ? thermal shutdown ? soft start ? break-before-make operation ? halogen-free according to iec 61249-2-21 definition ? compliant to rohs directive 2002/95/ec applications ? lcd tv, set top box and dvd player ? desktop pc and server ? add-in graphics board ? memory, fpga or p device power supplies ? point of load dc-to-dc conversion ? telecom and networking equipment typical application product summary input voltage range 4.75 v to 26 v output voltage range 0.6 v to 13.2 v operating frequency 500 khz continuous output current 4 a peak efficiency 93 % highside/lowside r ds_on 35 m /19 m package so-8 figure 1 - typical application circuit ena b le v i n v o controller boot v s w g n d fb comp e n v reg v i n 1 2 3 4 5 6 7 8 sic413
www.vishay.com 2 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 pin configuration functional block diagram figure 2. so-8 pin out - top view 1 2 3 4 8 7 6 5 fb v i n v reg g n d v s w boot e n comp pin description pin number symbol description 1comp error amplifier output. connects to the compensation network. 2 en chip enable pin. active high. connects to a po wer source through a 10k to100k resistor to enable. 3 boot connect to 0.1 f capacitor from v sw to boot to power the high side gate driver. 4v sw inductor connection. connect an output filter inductor to this pin. v sw is high impedance when the ic is in shutdown mode. 5 gnd ground pin. 6v in supply voltage. 7v reg internal regulator output. an external 4.7 f decoupling capacitor is required at this pin. 8 fb output voltage feedback input. ordering information part number package SIC413CB-T1-E3 so-8 (6.2 x 5 x 1.75 mm) sic413db reference board figure 3. functional block diagram e n u v lo v i n boot g n d control logic and acti v e dead time v s w sh u tdo w n control otp o v p fb v reg p w m gm f osc 5.5 v reg o v er c u rrent comp v reg
document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 3 vishay siliconix sic413 notes: a. t a = 25 c and all voltages referenced to gnd unless otherwise noted. stresses beyond those listed under "absolute maximum ratings" may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at thes e or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute ma ximum rating/conditions for extended peri ods may affect device reliability. notes: b. recommended operating conditions are specifi ed over the entire temperature range, and al l voltages referenced to gnd unless o therwise noted. c. peak value is specified for pulses 100 ns. absolute maximum ratings t a = 25 c, unless otherwise noted a parameter symbol min. max. unit input breakdown voltage v in - 0.3 28 v common switch node breakdown voltage v sw dc - 1 28 v sw peak c -1 30 logic inputs v comp , v fb , v en - 0.3 6 bootstrap voltage v boot - 0.3 33 maximum power dissipation p d 1.5 w operating temperature t j - 25 125 c storage junction temperature t stg - 40 150 soldering peak temperature 260 recommended operating conditions b parameter symbol min. typ. max. unit input voltage v in 4.75 12 26 v logic inputs v comp , v fb , v en 4.5 5 5.5 common switch node v sw dc - 0.3 12 26 v sw peak c - 0.3 24 28 thermal resistance ratings parameter symbol typ. unit junction-to-case resistance in operation, max. junction r thjc contact vishay for thermal design assistance c/w junction-to-ambient resistance pcb = copper 25 mm x 25 mm r thja case top to board edge pcb = evbsic413 rev. 3.0; no forced airflow r thca
www.vishay.com 4 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 notes: a. guaranteed by design and not 100 % production tested. b. pulse test; pulse width 300 ms, duty cycle 2 %. specifications parameter symbol conditions unless specified otherwise v in = 12 v, v en = 5 v, v out = 3.3 v, t a = 25 c min. typ. a max. unit converter operation output current a i out air flow = 0 4 a internal regulated voltage v reg 55.76.1v load regulation a 0 i o 4 a 0.6 % line regulation a i out = 0 0.1 %/v feedback voltage v fb t a = 25 c 0.591 0.6 0.609 v t a = - 25 c to 85 c 0.582 0.6 0.618 mosfet on resistance r ds(on)hs v boot - v sw = 5.5 v 35 m r ds(on)ls v reg = 5.5 v 19 internal oscillator frequency f osc 435 500 565 khz max. pwm duty cycle dc 62 70 % error amplifier open loop voltage gain 110 db unity gain bandwidth 2.5 mhz transconductance 1.5 ms input bias current i fb 2na max. sink/source current 30 a enable enable logic level high v en h v en rising 1.8 v enable logic level low v en l v en falling 0.6 protection overvoltage trip point ovp v fb rising and when v fb /v ref is greater than 115 120 125 % overvoltage trip hysteresis ovp hys v fb falling and when v fb /v ref is less than 110 v in undervoltage lockout v in uvlo-h v in rising 3.55 3.8 4.05 v v in undervoltage lockout hysteresis v in uvlo hs v in falling 200 mv thermal shutdown t j sd 165 c thermal shutdown hysteresis t j sd hs 20 peak current limit i lim 7a soft start soft start period t ss 5ms supply current input current i q v en = high and no load 10 ma shutdown current i sd v en = 0 v 8 a dynamic b rise time t r_sw 10 % to 90 % of sw 16 ns fall time t f_sw 90 % to 10 % of sw 15
document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 5 vishay siliconix sic413 electrical characteristics shut down current vs. temperature internal regulator voltage vs. temperature feedback voltage vs. temperature (normalized) i sd ( a) 0 2 4 6 8 10 12 14 16 - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) v i n = 12 v v reg ( v ) - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) 4.4 4.6 4. 8 5.0 5.2 5.4 5.6 5. 8 6.0 v i n =12 v /24 v v i n =4.75 v v fb ( n ormalized) - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) 0.990 0.995 1.000 1.005 1.010 v i n = 12 v maximum duty cycle vs. temperature frequency vs. temperature peak current limit vs. temperature (normalized) - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) 70 71 72 73 74 75 76 77 maxim u m d u ty cycle ( % ) v i n = 12 v s w itching fre qu ency (khz) - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) 470 4 8 0 490 500 510 520 530 v i n = 12 v i lim ( n ormalized) - 25 - 10 5 20 35 50 65 8 0 95 110 125 temperat u re (c) 0.6 0.7 0. 8 0.9 1 1.1 1.2 1.3
www.vishay.com 6 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 electrical characteristics efficiency at v in = 12 v load regulation at v in = 12 v, v o = 3.3 v load c u rrent (a) efficiency ( % ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 60 65 70 75 8 0 8 5 90 95 v o = 5.0 v v o = 3.3 v v o = 1. 8 v load c u rrent (a) o u tp u t v oltage ( v ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.335 3.340 3.345 3.350 3.355 3.360 3.365 set v o - 0.3 % act u al v o set v o + 0.3 % efficiency at v in = 5 v and v o = 1.8 v load regulation at v in = 12 v, v o = 5.0 v load c u rrent (a) efficiency ( % ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 60 65 70 75 8 0 8 5 90 95 load c u rrent (a) o u tp u t v oltage ( v ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.030 5.035 5.040 5.045 5.050 5.055 5.060 5.065 5.070 set v o - 0.3 % set v o + 0.3 % act u al v o
vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 7 electrical characteristics system starts up with en pin becoming high while v in is ready. v in = 12 v, v o = 3.3 v and i o is preset to about 3 a. resistive load. v o ripple and v sw switching waveform. v in = 12 v, v o = 3.3 v and l = 10 h (ihlp2525ez type). c o consists of mlcc of 4.7 f and tantalum of 100 f/20 v x 2 overcurrent protection at i o = 8 ~ 10 a. v in = 12 v, v o = 3.3 v and l = 10 h (ihlp2525ez type). c o consists of mlcc of 4.7 f and tantalum of 100 f/20 v x 2 comp: 500 mv/div v o : 1 v /div en: 2 v/div i l : 1 a/div t: 1 ms/div v sw : 5 v/div v o : 1 v/div v o : 20 mv/div i l : 1 a/div t: 500 ns/div comp: 500 mv/div i l : 5 a/div v sw : 10 v/div v o : 1 v/div t: 20 ms/div system shuts down with en pin becoming low. v in = 12 v, v o = 3.3 v and i o comes down from about 3 a. transient response. v in = 12 v, v o = 3.3 v and l = 10 h (ihlp2525ez type). c o consists of mlcc of 4.7 f and tantalum of 100 f/20 v x 2. output current steps up and down between 0.4 a and 4 a with less than 1 s rising and falling time. comp: 200 mv/div v o : 1 v/div en: 2 v/div i l : 1 a/div t: 200 s/div t: 50 s/div v o : 100 mv/div i l : 2 a/div
www.vishay.com 8 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 detailed operational description input voltage (v in ) the input voltage pin on the sic413cb provides the bias supply for the pwm controller ic and the mosfet driver circuitry. this pin also is inte rnally connected to the drain of the high side mosfet. feedback (fb) and output voltage (v o ) the fb pin is the negative input of the internal error amplifier. this pin connects to the center of the output voltage divider, through a 10k ~ 100k resistor (for noise isolation). when in regulation the fb voltage is 0.6 v. the output voltage v o is set based on the following formula. v o = v ref (1 + r1/r2) where r1 and r2 are shown in figure 4. enable (en) cmos logic signal. in the low state, the en pin shuts down the driver ic and disables both high-side and low-side mosfets. an internal pull up resistor will enable the device if this pin is left open. an external pull up of 10 k to 100 k is recommended for better noise immunity. soft-start (ss) this device allows typical 5 ms soft start time to prevent inrush current during system startup. the soft start cycle starts when en is asserted (low to high). under voltage lockout (uvlo) the sic413cb incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (v in ) is below x.xx v typical. during power up, internal circuits are held inactive until v in exceeds the nominal uvlo threshold voltage. once the uvlo rising threshold is reached, the device start-up begins. the device keeps operating unless v in drops below uvlo falling threshold. the nominal 200 mv uvlo hysteresis and 2.5 s rising and falling edge de-glitch circuit reduce the lik elihood of the device shutdown due to noise on v in . switch node (v sw ) the switch node is the inte rconnection between the and high- and low-side mosfets. connect the output inductor to this pin. also, this node is the return path for the bootstrap capacitor. bootstrap circuit (boot) a diode and a capacitor form a bootstrap circuit that powers high-side mosfet driver. sic413 has this diode built in and therefore only an external capacitor is required to form this circuit. this capacitor is c onnected between boot pin and v sw pin. over temperature protection (otp) otp provides thermal protection to the controller and power mosfets when an overload condition occurs. when the junction temperature of the sic413cb exceeds nominal 165 c (otp trip point), the pow er mosfets will be turned off and the controller will be disabled. the device will automatically restart when the junction temperature drops to nominal 20 c below its trip point. after the thermal protection is deasserted, a regular soft start cycle will be initiated. over voltage protection (ovp) when the feedback voltage on fb pin exceeds 120 % of v ref , the over voltage condition is asserted. when over voltage occurs, the controller will turn on low-side mosfet and turn off high-side mosfet to discharge the excessive output voltage. the over vo ltage condition is removed when the voltage on fb pin drops to below 110 % of v ref . over current protection (ocp) the sic413cb integrates all components required for over current protection. this achieved by sensing the current flowing through the low-side mosfet. when low-side mosfet is turned on, the current flowing through it will generate a voltage drop determined by its r ds(on) . after a blanking time delay (to ignore switching noise), this voltage is compared to a reference that corresponds to a preset overcurrent threshold (typical 7 a peak). if the voltage drop on low-side mosfet is higher than the preset reference, an overcurrent protection event o ccurs. this triggers the pwm controller to keep the low side mosfet on until the inductor current discharges to a level below the over current protection thres hold. this lowers t he duty cycle and causes the output voltage to droop. the sic413cb overcurrent fault mode is designed to protect against false triggering.an overcurrent event is defined as starting when the overcurrent threshold is tripped and ending when the inductor current in the low side mosfet is below the overcurrent trheshold. seven sequential overcurrent events are required to place the sic413cb into the over cur- rent fault mode. overcurrent events are counted by an up down counter. if the overcurrent state is detec ted, the counter counts 1 up otherwise it counts 1 down. if the count reaches 7, the device will enter fault mode and both high- and low-side mosfets will turn off for 15 pwm clock cycles. after this period, the device will initiate a regular soft start. this sequence repeats until the overcurrent is completely removed. this is often referred to as hiccup mode. if the counter does not reach the count of 7. the sic413cb does not enter into the overcurrent fault mode and operation is not disrupted. shoot-through protection (break-before-make: bbm) the sic413cb has an internal break-before-make function to ensure that both high- and low-side mosfets are not turned on at the same time. an internal circuit detects the falling edge of both high- and low-side gate drive. the low-side mosfet is turned on only after the high-side gate voltage is less than v bbm , similarly the high-side mosfet gate is turned on after a fixed dead- time after the low side gate is less than v bbm. this break- before-make time parameter is not user adjustable.
vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 9 application notes inductor selection the inductor is one of th e energy storage components in a converter. choosing an inductor means specifying its size, structure, material, inductance, saturation level, dc-resistance (dcr), and core loss. fortunately, there are many inductor vendors that of fer wide selections with ample specifications and test data, such as vishay dale. the following are some key parameters that users should focus on. in pwm mode, inductance has a direct impact on the ripple current. assuming 100 % efficiency, the steady state peak-to-peak inducto r (l) ripple current (i pp ) can be calculated as where f = switching frequency. higher inductance means lowe r ripple current, lower rms current, lower voltage ripple on both input and output, and higher efficiency, unless the re sistive loss of the inductor dominates the overall conduction loss. however, higher inductance also means a bigger inductor size and a slower response to transients. for fixed line and load conditions, higher inductance results in a lower peak current for each pulse, a lower load capabilit y, and a higher switching frequency. the saturation level is another important parameter in choosing inductors. note that the saturation levels specified in data sheets are maximum currents. for a dc-to-dc converter operating in pwm mode, it is the maximum peak inductor (i pk ) current that is relevant, and can be calculated using these equations: where i o = output current. this peak current varies with inductance tolerance and other errors, and the rated saturation level varies over temperature. so a sufficient design margin is required when choosing current ratings. a high-frequency core material, such as ferrite, should be chosen, the core loss could lead to serious efficiency penalties. the dcr should be kept as low as possible to reduce conduction losses. input capacitor selection to minimize input voltage ripple caused by the step-down conversion, and interference of large voltage spikes from other circuits, a low-esr input capacitor is required to filter the input voltage. the input capac itor should be rated for the maximum rms input current of: it is common practice to rate for the worst-case rms ripple that occurs when the duty cycle is at 50 %: output capacitor selection the output capacitor affects output voltage ripple due to 2 reasons: the capacitance and the effective series resistance (esr). the selection of the output capacitor is primarily determined by the capacitor esr required minimizing voltage ripple and current ripple. the relationship between output ripple v o , capacitance c o and its esr is: multiple capacitors placed in parallel may be needed to meet the esr requirements. however if the esr is too low it may cause stability problems. control loop design the sic413cb is an integrated voltage mode buck converter. the loop stability depends on input and output voltage, output lc filter, the equivalent lumped capacitance, resistance and inductance attached to the output voltage rail beyond the lc filter. the output lc filter creates a two pole roll-off of the loop gain that makes the closed loop system inherently unstable. therefore, a compensation network of poles and zeros must be implemented to achieve unconditional stability. figure 4 shows a simplified diagram of the sic413cb buck converter control loop and the external elements that affect loop gain, phase shift and stability. in this diagram l1, c4 and c5 and r6 form a first order model of low pass filter. resistor r6 represents the effe ctive series resistance (esr) of c5, which is often the ca se of a polymer (tantalum) capacitor. ceramic (mlcc) ca pacitors are also used as denoted by c4, which has near zero esr. to balance the performance and cost, the recommended output capacitor configuration is a combination of low cost, high capacitance polymer capacitors (c5) with esr (r6) to add a zero to help boost phase margin and mlcc capacitors (c4) that have low esr for achieving low voltage ripple. in practice, the lumped equivalent capacitance at the output of the filter may be a combination of many different kinds of capacitors. the characteristics of these capacitors must be considered when deriving the open loop transfer function and designing the loop compensation. it is important to have a good approximation of the lu mped impedance (capacitors, resistors, ferrite beads, filters, etc.) tied to the rail before calculating compensation net work component values. resistor r1 and r2 form the feedback voltage divider that samples the dc output and applies a feedback signal to the fb pin. components c1, c2, c3, r4, r5 and the transconductance error amplifier form the loop compensation network. with voltage mode control loop the () f l v v v v i i n o i n o pp . . - . = 2 pp o pk i i i+ = ) ( - = i n o i n o max o. rms v v v v i i1 2 .max. o rms i i= ) ( . . + . = o pp o c f esr i v 8 1
www.vishay.com 10 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 output voltage is fed back at t he fb pin. this feedback signal is summed with a precision voltage reference through a high bandwidth transconductance amplifier, often referred to as the error amplifier. this summation creates an error signal that is proportional to the difference between the actual output voltage and the desired output voltage, which is achieved when the voltage at th e center tap of the feedback resistor divider is equal to the voltage reference. the error signal is present at the comp pi n, which is the output of the error amplifier. the error amplifier in the sic413cb has a high loop gain and a 2.5 mhz gain bandwidth product. it is designed this way to provide fast transient response in applications such as dram memory arrays in graphics cards. this lets the control loop quickly respond to any deviation of the output voltage. it also makes the sic413cb more sensitive to noise on the fb pin. it is recommended to add resistor r3 at 20 k to help isolate the error amplifier from noise on the fb pin and give the designer the full benefit of the fast response time the sic413cb can deliver. under normal operation the output of the error signal varies between 1.0 v and 2.0 v. this corresponds to the peak to peak amplitude of the saw-t ooth wave form generated by the oscillator at the input to the pwm comparator. the pwm comparator drives the logic t hat controls th e mosfet gate drivers. these drivers control the turn on and turn off of the high- and low-side mosfets. as the error signal varies the pwm duty cycle is adjusted up and down to counteract the error. this interaction is normal load modulation and can be seen in a slight jitter on the trailing edge of the pwm signal. the resulting pwm signal at the vsw switching node is integrated by the lc filter to deliver the desired dc output voltage. very low steady state duty cycles occur when the desired output is much smaller than the input (i.e. 24 v input to 1.2 v output). in this case, the error signal will be closer to 1 v. very high duty cycles occur when the desired output is closer to the input (i.e. 5 v input to 3. 3 v output). in this case, the error signal is closer to 2 v. as can be seen, in these cases the error signal may have limited headroom for control under severe load transient conditions. this can result an asymmetrical transient respons e characteristic and slightly longer regulation recovery times for either the load acquisition or load shedding. open loop transfer function the following discussion derives the equations for the open loop transfer function. the technique for selecting the poles and zeros for optimized loop stability is then presented. for this analysis we are considering the lc filter approximation given in figure 4 and are not considering the impedance of the load. howe ver, most output impedances can be modeled using the lumped circuit approximation shown in figure 4. one exception is the use of a filter with a roll off frequency that is inside the loop bandwidth. in this case, derivation of the transfer function that includes the phase and gain effects of this filter is important. in some cases, filters can reduce gain margin and cause marginal stability if not considered thoroughly. the loop gain transfer function is broken into four blocks, each representing a different part of the buck converter. the four blocks and their frequen cy domain equations are as follows: block 1 - g lc : output lc filter cons isting of l1, c4, c5 and r6 block 2 - g sp : output voltage sampling network composed of c1, r1 and r2 block 3 - g pwm : pwm modulation gain that equals to v in / v osc , where v osc = saw tooth peak to peak voltage block 4 - g comp : amplifier compensator with components of c2, c3, r4, r5 and the amplifier gain g m , which is a function of frequency. resistor r4 value should be very large compared to r5. the purpose of r4 is to eliminate non-monotonic output behavior during rapidly pulsed off-then-on line transients. r4 provides a fast discharge path for c3 and resets the error signal at comp to zero before the line input pulses back on. ideally, r4 can be ignored for the purposes of the loop transfer function. ignoring r4 gives the following simplified transfer function for block 4. the overall open loop transfer function for this system, g ol , is then the product of the four transfer functions derived for each block. converting to the logarithm form we have sr6 ? c5 + 1 2 3 = l1 ? (c4 + c5) + sr6 ? c5 + 1 r6 ? c4 ? c5 ? l1 + s s g lc 1 1 r1 + r2 r1 ? r2 s+ r1 ? c1 s+ g sp ? c1 = osc i n p w m v g v = 1 ) 1 1 1 1 1 2 r4 ? r5 ? c2 ? c3 r5 ? c3 r4 ? c3 r5 ? c2 s r5 ? c2 s + c3 g g m comp + + + + s ( ? ? = 1 1 c2 + c3 c2 ? c3 r5 ? s+ r5 ? c2 s+ sc3 g g m comp ? = g ol = g lc ? g sp ? g p w m ? g comp g ol (db) = g lc (db) + g sp (db) + g p w m (db) + g comp (db)
vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 11 compensation considerations the criterion for unconditio nal stability of a closed loop system is that the open loop transfer function has the following attributes. 1. the magnitude of the open loop transfer function must cross through 0 db with a slope of - 20 db per decade 2. the phase shift of the open lo op transfer function must be at least 45 at the frequency, at which the magnitude of the loop gain crosses through 0 db 3. the phase shift should not be rapidly decreasing at loop gain slightly less than 0 db to determine if these criterion are met the bode plot of the transfer function is drawn. before drawing the bode plot, the poles and zeros need to be located. the following discussion serves as a guide to selectio n of the component values for the compensation network. the compensation process begins by selecting loop bandwidth. we recommend that the 0 db crossover frequency is set somewhere between 10 % and 20 % of switching frequency. the sic413cb has a fixed switching frequency of 500 khz. this means that the bandwidth of the loop can be set somewhere between 50 khz and 100 khz. this wide loop bandwidth, made possible by the ultra fast error amplifier in the sic413cb, can provide excellent transient response and load regulation. it can be seen that within the lc filter block, there are generally three poles (denoted p1, p2 and p3) and one zero (denoted z1). the double pole (p1 and p2) created by the lc filter is the dominant re sponse characteristic of the system. the locations of these poles and zero depend strongly on the types of capacitors used in the output filter. three cases will be analyzed as follows. case 1: output capacitors ar e a combination of those with esr (c5. e.g. polymer or tant alum type) and those with no esr or little esr (c4. e.g. ceramic type) the poles and zero for this case are as follows to meet the above stability crit erion, the frequency of the zero f z1 should be placed at a frequency lower than or equal to that at the double pole of f p1,p2 . pole f p3 should be located at a much higher frequency than f p1,p2 . this requirement sets the boundaries on the values of c4, c5 and r6. capacitor c4 has to be much smaller than c5. case 2: output capaci tor is all ceramic mlcc ignoring c5 and r6, the poles are as follows this output filter configuration can be challenging because there is no zero to help boost the phase shift that is introduced by the lc double pole. case 3: all capacitors have esr, no ceramics. ignoring c4 we have the following for the poles and zero this case is the best situatio n for loop comp ensation since no extra pole to add phase shift. the zero created with the esr also helps reverse phase shift added by the lc filter. in the output voltage feedba ck network block there is one pole (denoted p4) and one zero (denoted z2). the locations of the pole and zero are in this block c1 and r1 create the zero and c1 together with the parallel combination of r1 and r2 generates the pole. adding a capacitor in parallel wit h r2 is not effective here. it does not change the zero location and move the pole closer to this zero and cancels out its effect on phase margin. from figure 4 we can derive the dc expression for the output voltage. from this equation and the equations of the pole and zero locations, it can be seen that pole and zero locations of this block have the following relationship this relationship means that when the output voltage v o is approaching the chip reference voltage, v ref , the zero in the sampling network has diminishing effect on boosting the loop phase margin. in other words, t he value if adding c1 is more apparent when the output voltage is high relative to v ref and becomes smaller at lower outpu t voltages. therefore, the use of this capacitor is optional for low voltage conversions (e.g. 1.2 v output or lower). to make the zero f z2 work for compensation of the control loop it should to be placed at a frequency that is less than or equal to the frequency of the lc double pole location. block 3 is a dc transfer block and therefore has no pole and zero. it only affe cts the dc gain of open loop transfer function. this can affect phas e margin as increasing the dc loop gain can increase the loop bandwidth and reduce phase margin and visa versa. 2 1 l1 ? (c4 + c5) f p1,p2 2 ? c4 ? r6 1 f p3 2 ? c5 ? r6 1 f z1 2 1 l1 ? c4 f p1,p2, mlcc = p3, mlcc f and z1, mlcc f w ill not exist 2 1 l1 ? c5 f p1,p2,esr = p3,esr f does not exist 2 ? c5 ? r6 1 f z1,esr = 2 ? c1 ? (r1//r2) 1 2 ? 1 r1 + r2 r1 ? r2 f p4 = ? c1 = 2 ? c1 ? r1 1 f z2 = ref o v r2 r1 v ? =) (1 + ref o z2 p4 v v f f =
www.vishay.com 12 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 the amplifier compensation block is where the designer works hard to compensate the loop to achieve an unconditionally stable closed loop system. this block generally has two poles (denoted p5 and p6) and one zero (denoted z3) as shown in the equation. the locations of these poles and zero are to make the zero f z3 and pole f p6 work for increasing phase margin the zero should be placed at a frequency lower than and the pole much higher than the lc double pole frequency. in general, as soon as the output lc filter is determined, the dominant double pole is fixed. then the compensation design will be a "try and use" process based on above theory. usually a network analyzer is used to confirm the loop stability. to make a contro l system stable the solution is infinite, meaning there are lots of combinations of c1, c2, c3, r1, r4 and r5 that can make the system stable. but a designer's job is to find the optimized one that both makes the system stable and has th e best transient response. = 0 p5 f 2 ? r5 ? 1 c2 + c3 c2 ? c3 f p6 = 2 ? r5 ? c2 1 f z3 = figure 4. control and compensation network v o v ref = 0.6 v sa w tooth v i n v o transcond u ctance amplifier comparator + - - + high-side mosfet dri v er lo w -side mosfet dri v er r3 r2 c5 r1 q2 q1 c4 c3 c2 l1 c1 r5 r6 r4 1.0 v 2.0 v
vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 13 pcb layout as in the design of any switching dc-to-dc converter, a good pcb layout ensures successful transition from design to production. one of a few drawbacks of switching converters is the noise generated by the high frequency switching and coupled by parasitic inductance and capacitance. however, noise levels can be reduced or minimized if a pcb is well laid out. the following is a guidance on sic413 layout. input capacitors: c1 through to c6 are the input capacitors. they are placed side by side together to form a block and this block sits right beside sic413's v in and gnd pins. this placement minimizes the distance between v in pin, capacitors and chip?s ground, which minimizes the possibility of noise injected in v in pin. also the mlcc with smallest value (0.01 f) is placed closest to v in pin, and then mlcc with larger values (0.1 f, 10 f) and the last, the electrol ytic. this is because their esrs are getting larger and larger from small value mlcc to large value mlcc and then electrolytic capacitor. output capacitors: c17 through to c20 are the output capacitors. they are placed the same way as input capacitors. decoupling capacitors of v reg : c7 and c8, are placed right beside gnd pin on their negative sides. their positive sides are connected to the chip's v reg pin through two vias from the bottom of the pcb. the trace distance should be kept less than 10 mm. boot capacitor: c14 is the boot capacitor. r5 is added to allow flexibility for adjusting the high-side mosfet driving current to reduce possible noise. compensation network: c9, c10, r6 and r10 form this network. these components should be placed in a tight group. this group then should be in close proximity to the comp pin. trace lengths between the components should be minimized. output sampling network: r7, c15, r9 and r11 constitute the output voltage sampling network. these components should be placed in a tight grouping and in close proximity to the fb pin. since sic413 has only one gnd pin, this makes the chip more sensitive to noise coming from gnd. therefore r11 is added to perform as a filter to remove any possible noise from ground. grounding: separate analog and power ground paths are recommended for optimal noise reduction in the sic413cb converter. these grounds s hould both be connected at the gnd pin. connect the ground pin of the input and output capacitors to the power ground. connect the ground pin for the v reg decoupling caps, the compensation network grounds, and the output voltage sampling network grounds to the analog ground. it is preferred to use low inductance ground planes when ever possible. if single sided board is being used then try to keep the ground traces short and going a star configur ation at the gnd pin. power traces: the power path is formed starting at vin. it then branches to p gnd and v sw to v out . the trace thickness for the power path should be kept to a minimum of 50 mils. placement of components should focus on keeping these traces as short as possible to minimize parasitic inductance and resistances. they have minimum 50 mil trace width (at the v in pin area) and this segment is very short, which is good enough for the power level handled by this chip. figure 6 and figure 7 below show a recommended board layout for converters using sic413cb.
www.vishay.com 14 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 sic413 schematic for th e suggested pcb layout figure 5. reference board schematic v o e n v i n j4 v o_g n d 1 c4 10 f r11 20k c6 0.01 f c5 0.1 f j3 v o 1 c7 4.7 f j2 v i n _g n d 1 r5 0r j1 v i n j1 1 + c1 8 100 f + c2 10 f r6 6k65 u1 sic413 comp 1 e n 2 boot 3 v s w 4 fb 8 v reg 7 v i n 6 g n d 5 + c19 100 f + r 8 r + c17 100 f + c 8 0.1 f c14 0.1 f c20 4.7 f r10 750k r9 2k21 c3 10 f c10 10 nf + c1 100 f + r7 10k c9 100 pf c21 c r1 100k c15 3.3 nf l1 10 h c16 c
vishay siliconix sic413 document number: 69057 s09-2250-rev. d, 26-oct-09 www.vishay.com 15 suggested pcb layout figure 6. pcb layout - top layer figure 7. pcb layout - bottom layer bill of materials for the suggested pcb layout v in = 12 v, v out = 3.3 v item qty reference part voltage pcb footprint part number manufacturer 1 1 c1 100 f 35 v d6.3x11.2-d0.6x2.5 eca-1vhg101i panasonic 2 3 c2, c3, c4 10 f 25 v sm/c_1210 tmk325b7106mn-t taiyo yuden 3 3 c5, c8, c14 0.1 f 50 v sm/c_0603 vj0603y104kxacw1bc vishay 4 1 c6 0.01 f 50 v sm/c_0402 vj0402y103kxacw1bc vishay 5 1 c7 4.7 f 10 v sm/c_0805 lmk212b7475kg-t taiyo yuden 6 1 c9 100 pf 50 v sm/c_0603 vj0603y102kxacw1bc vishay 7 2 c10, c15 3.3 nf 50 v sm/c_0603 vj0603y333kxacw1bc vishay 8 2 c16, c21 not populated 50 v sm/c_0603 vishay 9 1 c17 100 f 20 v 595d-d 595d107x9020d2t vishay 10 2 c18, c19 100 f 20 v 595d-d 595d107x9020d2t vishay 11 1 c20 4.7 f 16 v sm/c_1206 c3216x7r1c106m tdk 12 1 j1 v in probe hook 1540-2 keystone 13 1 j2 v in_gnd probe hook 1540-2 keystone 14 1 j3 v o probe hook 1540-2 keystone 15 1 j4 v o_gnd probe hook 1540-2 keystone 16 1 l1 10 h ihlp2525 ihlp2525ezer100m01 vishay 17 1 r1 100k 50 v sm/c_0603 crcw0603100kfkea vishay 18 1 r5 0r 50 v sm/c_0603 crcw06030000fkea vishay 19 1 r6 6k65 50 v sm/c_0603 crcw06036k65fkea vishay 20 1 r7 10k 50 v sm/c_0603 crcw060310k0fkea vishay 21 1 r8 not populated 50 v sm/c_0603 vishay 22 1 r9 2k21 50 v sm/c_0603 crcw06032k21fkea vishay 23 1 r10 750k 50 v sm/c_0603 crcw0603750kfkea vishay 24 1 r11 20k 50v sm/c_0603 crcw060320k0fkea vishay 25 1 u1 sic413 so-8 sic413 vishay
www.vishay.com 16 document number: 69057 s09-2250-rev. d, 26-oct-09 vishay siliconix sic413 package dimensions soic (narrow): 8-lead jedec part number: ms-012 vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69057 . dim. millimeters inches min. max. min. max. a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 figure 10. so-8 dimensions 4 3 1 2 5 6 8 7 h e h x 45 c all leads q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (gage plane) s
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

▲Up To Search▲

Price & Availability of SIC413CB-T1-E3

	To Download SIC413CB-T1-E3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .